High-frequency circuit device and detection system

ABSTRACT

A high-frequency circuit device includes: a chip which includes a high-frequency element, a high-frequency circuit, a signal conductor, and a chip ground; a package substrate on which the chip is disposed, a shunt path which is constituted by a package signal conductor which is disposed on an upper surface of the package substrate and is electrically connected to the signal conductor, a package first ground which is electrically connected to the chip ground, and a shunt element which is electrically connected to the package signal conductor and the package first ground; and a package second ground which is disposed at least inside the base of the package substrate or on a back surface of the package substrate, wherein a part of the base, a part of the shunt path, and the package second ground constitute a capacitive structure.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a high-frequency circuit device and adetection system which handle an electromagnetic wave. In particular,the present invention relates to an antenna device which transmits orreceives an electromagnetic wave.

Description of the Related Art

There is a high-frequency circuit device which handles anelectromagnetic wave including at least a part of a frequency band froma millimeter wave to a terahertz wave (at least 30 GHz and not more than30 THz) (hereinafter simply referred to as “terahertz wave”). As anexample of the high-frequency circuit device, Japanese PatentApplication Publication No. 2020-136910 discloses an oscillator in whicha negative resistance element and a resonance circuit are integrated ona semiconductor chip.

The high-frequency circuit device in Japanese Patent ApplicationPublication No. 2020-136910 uses a resonant tunneling diode (RTD) as thenegative resistance element, and has a circuit which supplies a biasvoltage to the negative resistance element (hereinafter simply referredto as “voltage bias circuit”).

Japanese Patent Application Publication No. 2020-136910 discloses atechnique in which, in order to suppress parasitic low-frequencyoscillation of an electromagnetic wave other than the terahertz wave(hereinafter simply referred to as “parasitic oscillation”), a shuntelement in which a resistance element and a capacitive element areconnected in series is electrically connected in parallel to the voltagebias circuit, and the parasitic oscillation is thereby suppressed.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above problem, andsuppresses parasitic oscillation.

A first aspect of the present invention is a high-frequency circuitdevice including: a chip which includes a high-frequency element, ahigh-frequency circuit, a signal conductor, and a chip ground; and apackage substrate which includes a base having an upper surface and aback surface on an opposite side of the upper surface, and on which thechip is disposed, the high-frequency circuit device further comprising:a shunt path which is constituted by a package signal conductor which isdisposed on the upper surface of the package substrate and iselectrically connected to the signal conductor, a package first groundwhich is electrically connected to the chip ground, and a shunt elementwhich is electrically connected to the package signal conductor and thepackage first ground; and a package second ground which is disposed atleast inside the base of the package substrate or on the back surface ofthe package substrate, wherein a part of the base, a part of the shuntpath, and the package second ground constitute a capacitive structure.

Further features of the present invention will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a top view and a cross-sectional view of ahigh-frequency circuit device according to a first embodiment;

FIGS. 2A and 2B are a top view and a cross-sectional view of thehigh-frequency circuit device according to a modification of the firstembodiment;

FIG. 3 is an equivalent circuit diagram of the high-frequency circuitdevice according to the first embodiment;

FIG. 4 is an equivalent circuit diagram of the high-frequency circuitdevice having a conventional configuration;

FIGS. 5A and 5B are a top view and a back surface view of thehigh-frequency circuit device according to a second embodiment;

FIGS. 6A and 6B are cross-sectional views of the high-frequency circuitdevice according to the second embodiment;

FIG. 7 is a cross-sectional view of the high-frequency circuit deviceaccording to the second embodiment;

FIG. 8 is an equivalent circuit diagram of the high-frequency circuitdevice according to the second embodiment;

FIGS. 9A and 9B show analysis examples of the high-frequency circuitdevice according to the second embodiment;

FIGS. 10A and 10B are graphs each showing a measurement result ofparasitic oscillation of the high-frequency circuit device according tothe second embodiment;

FIGS. 11A to 11C are cross-sectional views of the high-frequency circuitdevice according to a modification of the second embodiment;

FIG. 12 is a cross-sectional view of the high-frequency circuit deviceaccording to a third embodiment;

FIGS. 13A to 13C are cross-sectional views of the high-frequency circuitdevice according to a modification of the third embodiment;

FIGS. 14A and 14B are cross-sectional views of the high-frequencycircuit device according to a fourth embodiment; and

FIG. 15 is a cross-sectional view of the high-frequency circuit deviceaccording to a fifth embodiment.

DESCRIPTION OF THE EMBODIMENTS

With only an improvement in the layout of a resistance element and acapacitive element constituting a shunt element disposed on the surfaceof a circuit board, inductance caused by a physical distance becomes arestriction. Specifically, in the case where the shunt element isdesigned with a lumped constant circuit, it becomes difficult to controlthe inductance due to restrictions by an element size and a design ruleof a substrate and, for example, the impedance increases at 10 MHz orhigher. As a result, the possibility of occurrence of parasiticoscillation in a frequency range of not less than 10 MHz is increased.

From this, in a high-frequency circuit device aimed at a terahertz wave,it is desired to suppress an increase in the impedance of the circuit tosuppress the parasitic oscillation in a frequency range in which it isdifficult to perform control with the lumped constant circuit.

Hereinbelow, embodiments of the present invention will be described withreference to the drawings. Note that the present invention is notlimited to the following embodiments.

First Embodiment

A high-frequency circuit device according to a first embodiment will bedescribed by using FIGS. 1A and 1B to FIG. 4 .

Each of FIGS. 1A and 1B is a view showing a schematic configuration ofthe high-frequency circuit device according to the present embodiment.FIG. 1A is a top view, and FIG. 1B is a cross-sectional view taken alongthe line A-A′.

A high-frequency circuit device 100 according to the present embodimentis constituted by a package 192, a chip 191 mounted on the package 192,and a voltage bias circuit 180 which drives the chip 191 via the package192.

As shown in FIG. 1A, the rectangular chip 191 in which a high-frequencyelement 101 and a high-frequency circuit 102 accompanying thehigh-frequency element 101 are disposed is mounted on a packagesubstrate 112 constituting the package 192.

The chip 191 is mounted in a cavity 110 provided in the package 192. Thehigh-frequency element 101 is an active element which operates with aterahertz wave such as a transistor or a diode. The high-frequencycircuit 102 is a circuit of a passive element aimed at the terahertzwave such as a filter or an antenna. Many high-frequency circuits 102are constituted by distributed constant circuits. The terahertz wave isan electromagnetic wave including a frequency band which is at least apart of a frequency band from a millimeter wave to the terahertz wave(at least 30 GHz and not more than 30 THz) (hereinafter simply referredto as “terahertz wave”).

Further, the chip 191 may have an in-chip shunt element for stabilizingoperations of the high-frequency element 101 and the high-frequencycircuit 102. For example, the in-chip shunt element is constituted by achip resistance element 128 and a chip capacitive element 127. Inaddition, the chip 191 may include a chip signal pad (chip-side signalpad) 106 which applies a bias voltage to the chip 191 and a chip groundpad (not shown) which applies a ground voltage to the chip 191. Each ofthe chip signal pad 106 and the chip ground pad is formed of aconductive material. In the following description, it is assumed thatpads, grounds, and patterns are formed mainly of a conductive material.The chip signal pad 106 and the chip ground pad are provided forelectrical connection with an external circuit of the chip 191, and areprovided for, e.g., supplying a predetermined voltage from the outside.In addition, the chip signal pad 106 and the chip ground pad can beprovided for supplying a predetermined voltage to the external circuit.In the present embodiment, the predetermined voltage can be a groundvoltage, a power supply voltage, and a voltage from the voltage biascircuit. The high-frequency element 101 and the high-frequency circuit102 are disposed substantially at the center of the chip 191, and thechip capacitive element 127 described later is disposed adjacentthereto.

FIG. 1B is a cross-sectional view taken along the line A-A′ of FIG. 1A.In addition to the components described thus far, the chip 191 has atleast a dielectric layer 104, a chip signal pattern (chip signalconductor) 105, a chip ground 103, a semiconductor substrate 109, and aback surface chip ground 107. The dielectric layer 104 is constituted bya first dielectric layer 104 a and a second dielectric layer 104 b.

The chip signal pattern 105 is disposed between the first dielectriclayer 104 a and the second dielectric layer 104 b. The high-frequencycircuit 102 and the chip signal pattern 105 are electrically connectedto each other via a signal through conductor 120.

The chip signal pattern 105 is electrically connected to the chip signalpad 106. Alternatively, a part of the chip signal pattern 105 serves asthe chip signal pad 106.

The high-frequency element 101 is electrically connected to thehigh-frequency circuit 102 and the chip ground 103. The chip ground 103is electrically connected to the back surface chip ground 107 via a chipground through conductor 108. For example, a chip ground pad which isnot shown is provided on the same surface as that of the chip signal pad106. The chip ground pad which is not shown is electrically connected toa package-side ground pad. The chip ground pad which is not shown iselectrically connected to the chip ground 103.

For example, the chip capacitive element 127 is constituted by a part ofa chip shunt pattern (chip shunt conductor) 137 which is a conductor, apart of the second dielectric layer 104 b, and a part of the chip ground103. The chip capacitive element 127 is disposed adjacent to thehigh-frequency circuit 102. In addition, in FIG. 1A, the chip capacitiveelement 127 is disposed so as to surround the high-frequency circuit102, whereby it is possible to increase a layout area of the chipcapacitive element 127 on the chip 191, and secure a larger capacitance.

In addition, the chip capacitive element 127 is disposed so as to bedivided into portions on sides of two opposing sides of the chip 191(the right side and the left side of the chip 191 in FIG. 1A) such thatthe high-frequency circuit 102 is sandwiched by the chip capacitiveelement 127. With this, it is possible to dispose the chip resistanceelement 128, the chip signal pattern 105, and the chip signal pad 106 ina portion in which the chip capacitive element 127 is not disposed (theupper side of the chip 191 in FIG. 1A), and hence it is possible toreduce a chip size of the chip 191.

As the chip capacitive element 127, it is possible to use ametal-insulator-metal (MIM) capacitor in which an insulating layer issandwiched between metal layers. It is possible to use a wiring layer inthe chip 191 as the metal layer, and it is possible to use an insulatinglayer or a dielectric layer which forms the high-frequency circuit 102as the insulating layer. According to the present embodiment, as shownin FIG. 1B, the chip ground 103 is used as one of electrodes of the MIMcapacitor, and the chip ground 103 is connected to the back surface chipground 107 which applies a ground voltage via the chip ground throughconductor 108. The ground voltage may also be applied from a chip groundpad which is not shown. At this point, the chip ground pad iselectrically connected to the chip ground 103 via the chip groundthrough conductor 108.

A part of the chip shunt pattern 137 is used as the other electrode ofthe MIM capacitor via the second dielectric layer 104 b. In addition,the other electrode of the MIM capacitor may be connected to the chipresistance element 128 via wiring or a through conductor which is notshown. By constituting the MIM capacitor as the chip capacitive element127, it is possible to form the capacitance in the chip 191 with asimple manufacturing process.

The configuration of the chip capacitive element 127 is not limitedthereto. In addition to the configuration described above, it ispossible to use a configuration in which a capacitance is formed on asubstrate which is separate from the chip 191, and the capacitance isstuck to the surface or the back surface of the chip 191. According tothis configuration, it is possible to provide a capacitive elementhaving a larger capacitance.

As shown in FIGS. 1A and 1B, one terminal of the chip resistance element128 is connected to the chip shunt pattern 137 which is one terminal ofthe chip capacitive element 127 via wiring and a through conductor whichare not shown. The other terminal of the chip resistance element 128 isconnected to the chip signal pad 106 via the chip signal pattern 105.The chip resistance element 128 and the chip capacitive element 127 areconnected in series between the chip signal pattern 105 and the chipground 103. The chip resistance element 128 is preferably disposed inthe vicinity of the chip capacitive element 127 for easy connection withthe chip capacitive element 127. Alternatively, the chip resistanceelement 128 may also be disposed so as to be overlapped on the chipcapacitive element 127. The chip signal pattern 105 applies a biasvoltage to the high-frequency circuit 102.

The chip resistance element 128 and the chip capacitive element 127function as the shunt element for the high-frequency circuit 102.Specifically, the chip resistance element 128 and the chip capacitiveelement 127 which serve as the shunt element constitute a snubbercircuit. In the present embodiment, while the chip resistance element128 is connected to the side of the chip signal pad 106 and the chipcapacitive element 127 is connected to the side of the chip ground 103,the connection relationship may be reversed. In FIGS. 1A and 1B, thenumber of pairs of the chip resistance element 128 and the chipcapacitive element 127 is two, but the number of pairs thereof is notlimited thereto. It is only required that, at the frequency of parasiticoscillation to be suppressed, a resistance component of the shuntelement is smaller than an absolute value of a resistance component ofthe high-frequency element 101 constituting the high-frequency circuit102.

In addition, the chip resistance element 128 may also be constituted byusing a wiring resistance. With this, it is possible to reduce thenumber of components used in the chip 191 and implement a reduction inthe size of the chip 191. Further, the shunt element may also beconstituted by one of the chip resistance element 128 and the chipcapacitive element 127. In the case where the shunt element includes thechip capacitive element 127, it becomes possible to suppress not onlythe parasitic oscillation but also power consumption by cutting a directcurrent by utilizing frequency characteristics of an impedance.

The high-frequency element 101 is an element which operates in aterahertz wave region. The material of the semiconductor substrate 109is selected according to the structure of the high-frequency element101. For example, it is possible to use a silicon substrate or an InPsubstrate which is a compound semiconductor as the semiconductorsubstrate 109. In addition, the first dielectric layer 104 a and thesecond dielectric layer 104 b which constitute the dielectric layer 104are preferably formed of a substance having a low loss to the terahertzwave. For example, materials such as benzocyclobutene (BCB), siliconoxide, and silicon nitride can be used. The types of the materials arenot limited thereto.

In FIGS. 1A and 1B, the package 192 includes a resistance element 121and a capacitive element 122 which constitute a shunt element 140. Inaddition, the package 192 includes a package-side signal pad 118 forconnection with the chip-side signal pad 106 of the chip 191, and apackage-side ground pad 113 for connection with a chip-side ground pad(not shown) of the chip 191.

The package-side signal pad 118 and the package-side ground pad 113 areprovided for electrical connection with an external circuit. Each of thepackage-side signal pad 118 and the package-side ground pad 113 isconstituted by a conductive material. Herein, the external circuit isthe chip 191.

The package 192 also includes a bias connection terminal 181 to which abias voltage is supplied from the voltage bias circuit 180, and a groundconnection terminal 182 which provides a ground voltage. For reducingthe size of the package 192, it is preferable to use surface mountdevices (SMD) as the resistance element 121 and the capacitive element122. Wiring disposed in the package 192 also has a resistance value, andhence a wiring resistance included in the shunt element 140 may be usedas the resistance element 121. With this, it is possible to reduce thenumber of components used in the package 192 and implement a reductionin the size of the package 192.

The voltage bias circuit 180 is connected via the bias connectionterminal 181 and the ground connection terminal 182 from the outside ofthe package 192. Note that, instead of this configuration, the voltagebias circuit 180 may be disposed on the package 192 and may also bedisposed on the chip 191.

The chip-side signal pad 106 of the chip 191 and the package-side signalpad 118 of the package 192 are connected by a bonding wire 117. In orderto reduce the inductance of the bonding wire 117, it is preferable todispose the chip-side signal pad 106 and the package-side signal pad 118such that the chip-side signal pad 106 and the package-side signal pad118 are positioned close to each other, and reduce the length of thebonding wire 117. In order to shorten the bonding wire 117, it isappropriate to dispose the chip-side signal pad 106 at an end portion ofthe chip 191. In addition, it is appropriate to dispose the chip-sidesignal pad 106 and the package-side signal pad 118 such that thechip-side signal pad 106 and the package-side signal pad 118 face eachother with a side of the chip 191 interposed therebetween. It is alsopossible to control the inductance of the bonding wire 117 with thenumber of wires and the diameter of the wire. At the frequency of theterahertz wave or the parasitic oscillation to be suppressed, theresistance component of the bonding wire 117 is designed to besufficiently smaller than the absolute value of the resistance componentof the high-frequency element 101 constituting the high-frequencycircuit 102.

In FIGS. 1A and 1B, the package 192 has a package ground 115 on the backsurface side of the package 192. The package ground 115 has the samepotential as that of each of the package-side ground pad 113 and theground connection terminal 182. The back surface chip ground 107 of thechip 191 is electrically connected to the package ground 115 via aconductive layer 111. As the conductive layer 111, it is possible to usea low-resistance die bonding material. With this connection, the package192 supplies a ground voltage to the chip 191. Note that, with regard tothe supply of the ground voltage from the package 192, the groundvoltage may be supplied to a chip-side ground pad which is not shown viathe package-side ground pad 113.

One terminal of the resistance element 121 is connected to one terminalof the capacitive element 122 via a package intermediate wiring pattern(package intermediate wiring conductor) 124 which is a conductor. Thatis, the resistance element 121 and the capacitive element 122 areconnected in series. Consequently, it is preferable to dispose theresistance element 121 and the capacitive element 122 such that theresistance element 121 and the capacitive element 122 are positionedclose to each other. More preferably, one terminal of the resistanceelement 121 is disposed adjacent to one terminal of the capacitiveelement 122. With this, it is possible to reduce the length of thepackage intermediate wiring pattern 124 and reduce the inductance.

The other terminal of the resistance element 121 is connected to thepackage-side signal pad 118 and the bias connection terminal 181 via apackage signal pattern (package signal conductor) 123 which is aconductor. In addition, the other terminal of the capacitive element 122is connected to the package-side ground pad 113 and the groundconnection terminal 182 via a package first ground 125. A direction inwhich one terminal and the other terminal of the resistance element 121and one terminal and the other terminal of the capacitive element 122are aligned is preferably made identical to a direction in which thepackage-side signal pad 118 and the package-side ground pad 113 arealigned. With such a layout, it is possible to shorten wiring forconnection, and reduce the inductance.

The shunt element 140 is constituted by the resistance element 121 andthe capacitive element 122 which are connected in series, and functionsas the shunt element for the chip 191 including the high-frequencycircuit 102. Specifically, the resistance element 121 and the capacitiveelement 122 which serve as the shunt element constitute a snubbercircuit. In the present embodiment, the resistance element 121 isconnected to the side of the package signal pattern 123, and thecapacitive element 122 is connected to the side of the package firstground 125. Note that this connection relationship may be reversed. Inaddition, a plurality of the shunt elements 140 may be used. At thefrequency of the parasitic oscillation to be suppressed, the resistancecomponent of the shunt element 140 is preferably smaller than theabsolute value of the resistance component of the high-frequency element101 constituting the high-frequency circuit 102 of the chip 191. Inaddition, the shunt element 140 may be constituted by one of theresistance element 121 and the capacitive element 122. In the case wherethe shunt element 140 includes the capacitive element 122, it becomespossible to suppress not only the parasitic oscillation but also powerconsumption by cutting a direct current by utilizing frequencycharacteristics of the impedance.

In the package substrate 112 constituting the package 192, it ispossible to use a base used in a printed circuit board such as a glasscomposite substrate, a glass epoxy substrate, or a fluorine substrate.In addition, in the package substrate 112, it is possible to use a baseused in a ceramic circuit board such as an aluminum oxide (Al₂O₃)substrate, an aluminum nitride (AlN) substrate, or a low temperatureco-fired ceramics (LTCC) substrate. Preferably, a base having a low lossto the terahertz wave is used in the package substrate 112.

With regard to a positional relationship of individual components of thehigh-frequency circuit device 100, the shunt element of the chip 191 ispreferably disposed between the high-frequency circuit 102 and thevoltage bias circuit 180. In addition, the shunt element 140 of thepackage 192 is preferably disposed between the shunt element of the chip191 and the voltage bias circuit 180. The detail of a device which usesa plurality of shunt elements is disclosed in, e.g., Japanese PatentApplication Publication No. 2020-136910. Herein, a plurality of theshunt elements are used. With this, it is possible to suppress theparasitic oscillation in a wide frequency band.

According to our studies, in the case where the shunt element isdesigned with a lumped constant circuit, a frequency at which control ofthe inductance becomes difficult due to restrictions by an element sizeand a design rule of a substrate has been determined. For example, theimpedance of the circuit is expected to be increased at a frequency ofnot less than 10 MHz, and hence it is desirable to improve stability ofthe circuit at this frequency (not less than 10 MHz).

To cope with this, in the present embodiment, the high-frequency circuitdevice 100 has the following configuration. As has been described thusfar, the chip 191 has at least the high-frequency element 101, thehigh-frequency circuit 102, the chip signal pattern 105, and the chipground 103. The package 192 includes the base having the upper surfaceand the back surface which faces the upper surface (on the opposite sideof the upper surface), and has at least the package substrate 112 onwhich the chip 191 is disposed. In addition, as shown in FIG. 1B, thepackage 192 is characterized in that a capacitive structure 126 isprovided in a thickness direction of the package substrate 112 in thevicinity of a side on which the package 192 is connected to the chip191.

The capacitive structure 126 will be described. In FIG. 1B, thecapacitive structure 126 is constituted by a part of the base of thepackage substrate 112, a part of a shunt path 130, and a part of apackage second ground 114.

The shunt path 130 is defined as a path including the package signalpattern 123, the resistance element 121 constituting the shunt element140, the package intermediate wiring pattern 124, the capacitive element122 constituting the shunt element 140, and the package first ground125. The path of the shunt path 130 can also be defined as a paththrough which current passes. The shunt path 130 is disposed on theupper surface of the package substrate 112. The package signal pattern123 is electrically connected to the chip signal pattern 105. Thepackage first ground 125 is electrically connected to the chip ground103. The shunt element 140 is electrically connected to the packagesignal pattern 123 and the package first ground 125.

The package second ground 114 is a conductor disposed on the backsurface side of the package substrate 112 constituting the package 192.Herein, the package second ground 114 is electrically connected to thepackage ground 115 via a ground connection pattern (ground connectionconductor) 183. The ground connection pattern 183 is a thin line patternof a conductor. For example, the thin line pattern of the conductor canbe viewed as an inductor, and an impedance increases as a frequencyincreases. In other words, it is possible to adjust the impedance at adesired frequency. By utilizing this characteristic, in any band fromthe frequency of the parasitic oscillation to the frequency of theterahertz wave, the package ground 115 and the package second ground 114are electrically separated from each other by the ground connectionpattern 183. The ground connection pattern 183 may also be a filterconstituted by a distributed constant circuit.

In addition, the package second ground 114 is electrically connected tothe package first ground 125 via a package ground through conductor 116inside the package substrate 112. With the shape of the package groundthrough conductor 116, it is possible to impart an inductor componentand a capacitive component to the package ground through conductor 116.In other words, it is possible to adjust the impedance at a desiredfrequency. By utilizing this characteristic, for example, in any bandfrom the frequency of the parasitic oscillation to the frequency of theterahertz wave, the package first ground 125 and the package secondground 114 are electrically separated from each other. In a frequencyrange serving as a target, by electrically separating the individualgrounds, it is possible to prevent mixing of an unnecessary signal viathe ground, and hence the operation of the high-frequency circuit device100 is stabilized. By configuring a part of the base of the packagesubstrate 112 such that the conductor of the shunt path 130 and thepackage second ground 114 are sandwiched, as shown in FIG. 1B, it ispossible to provide a capacitance Cs and an admittance Gs in thevicinity of a connection portion between the chip 191 and the package192. In the present embodiment, this capacitive structure 126 is used asthe shunt element, and the capacitance obtained by the shunt element isused for suppressing the parasitic oscillation.

In each of the through conductors described above such as the chipground through conductor 108, the package ground through conductor 116,and the signal through conductor 120, after a through hole is formed ina member, an insulating film for electrical separation is formed on aninner wall of the through hole. Subsequently, by filling the throughhole with copper or the like which has low electrical resistance andallows easy electrode formation by electroplating or the like, each ofthese through conductors is formed. In addition, these conductors mayalso be smoothed by using chemical mechanical polishing (CMP) processingor the like. For example, after the through conductor is formed, a padmay be formed so as to be electrically connected to external wiring.

It is possible to adjust the capacitance obtained by the capacitivestructure 126 with an interval between the conductor of the shunt path130 and the package second ground 114. For example, as shown in FIG. 2B,the package second ground 114 may be disposed inside the base of thepackage substrate 112. In FIG. 2B, the package second ground 114 iselectrically connected to the package first ground 125 and the packageground 115 via the package ground through conductor 116. At this point,in any band from the frequency of the parasitic oscillation to thefrequency of the terahertz wave, the package first ground 125, thepackage second ground 114, and the package ground 115 are electricallyseparated from each other in the thickness direction of the base of thepackage substrate 112. By disposing the package second ground 114 insidethe base of the package substrate 112, flexibility of the capacitanceadjustment of the capacitive structure 126 is increased. As a result,controllability of parasitic oscillation suppression is improved.

According to FIGS. 1A and 1B and FIGS. 2A and 2B, when viewed from theshunt path 130, a part of the shunt path 130, a part of the packagefirst ground 125, and a part of the package second ground 114 aredisposed so as to overlap each other. Consequently, it can be said thatthe capacitive structure 126 serving as the shunt element and the shuntelement 140 constituted by the SMD component are disposed so as tooverlap each other when viewed from the shunt path 130. Thus, bydisposing a plurality of the shunt elements such that the shunt elementsoverlap each other, it is possible to reduce the length of wiringrequired by the circuit, and hence the suppression of the parasiticoscillation is facilitated. In addition, it is possible to dispose aplurality of the shunt elements such that the shunt elements overlapeach other, and hence a reduction in the size of the entire circuit isfacilitated, and it is possible to contribute to a reduction in the sizeof the package 192.

In addition, in FIGS. 1A and 1B and FIGS. 2A and 2B, in order to use thecapacitive structure 126 as the shunt element, a distance L between thehigh-frequency element 101 and the package ground through conductor 116preferably satisfies a relationship of λ_(sig)≤L≤λ_(para) between awavelength λ_(sig) and a wavelength λ_(para). Herein, the wavelengthλ_(sig) is an effective wavelength of a high-frequency signal of thehigh-frequency circuit 102, and the wavelength λ_(para) is an effectivewavelength of the parasitic oscillation which occurs in the shunt path130. The distance L is, e.g., a length along a current path from an endof the high-frequency element 101 (an end of an array antenna; an end ofan element close from a pad of an electrode) to the center of thepackage ground through conductor 116. Note that the effective wavelengthof the parasitic oscillation is long, and hence, even when an error ispresent at a position of a start point or an end point of the distanceL, an influence of the error is small.

FIG. 3 is a view showing an example of an equivalent circuit of thepresent embodiment. Specifically, the example of the equivalent circuitof each of FIGS. 1A and 1B is shown. In FIG. 3 , r₁₀₁ denotes anabsolute value of a negative resistance of the high-frequency element101. In general, when a combined resistance of circuits connected inparallel to the high-frequency element 101 is denoted by R, in the casewhere a relationship of r₁₀₁<R is satisfied, the circuit in a subsequentstage becomes unstable, and the parasitic oscillation easily occurs. Thechip 191 is connected to the package 192 via the chip-side signal pad106 and the conductive layer 111. Z₁₀₂ denotes a combined impedance ofthe high-frequency circuit 102. R₁₂₈ denotes a resistance of the chipresistance element 128. C₁₂₇ denotes a capacitance (electrostaticcapacity) of the chip capacitive element 127. R₁₂₈ and C₁₂₇ constitutethe snubber circuit which is the shunt element, suppress the influenceof the circuit of the package 192 when viewed from the high-frequencycircuit 102, and suppress, e.g., the parasitic oscillation on the sideof a high frequency of several GHz to several hundred GHz.

The chip-side signal pad 106 of the chip 191 and the package-side signalpad 118 of the package 192 are connected to each other via the bondingwire 117. L₁₁₇ denotes an inductance of the bonding wire 117.

With regard to the package 192, L_(line) expresses an influence ofcircuits or wiring provided in the shunt path 130 as an inductance. Thewiring in the shunt path 130 denotes the package signal pattern 123, thepackage intermediate wiring pattern 124, and the package first ground125. As has been described thus far, in the present embodiment, thecapacitive structure 126 is constituted by a part of the base of thepackage substrate 112, a part of the shunt path 130, and the packagesecond ground 114. Cs denotes a capacitance of the capacitive structure126. Gs denotes an admittance which is the reciprocal of the resistancecomponent of the capacitive structure 126.

The package second ground 114 which regulates a reference potential ofthe capacitive structure 126 is electrically connected to the packagefirst ground 125 via the package ground through conductor 116. Inaddition, the package first ground 125 is electrically connected to theconductive layer 111 of the chip 191 via the ground connection pattern183. While the potentials of these grounds are identical to each otherin terms of direct current, the grounds are separated from each other interms of alternating current depending on frequency, and unnecessarynoises or signals are thereby prevented from being combined with thecircuit via the grounds. Cs and Gs of the capacitive structure 126constitute the shunt element. Cs and Gs of the capacitive structure 126suppress mainly an influence of the inductor L_(line) caused by thecircuit or the wiring in the shunt path 130, and adjust the impedance ofthe shunt path 130 to a low impedance (an impedance of not more than apredetermined value) in a desired frequency range. This frequency rangeis, e.g., a range of at least 10 MHz and not more than 10 GHz (mediumfrequency range), and the parasitic oscillation in the medium frequencyrange is suppressed by adjusting the impedance of the shunt path 130 tothe low impedance in the medium frequency range.

The shunt path 130 has the shunt element 140 constituted by the SMDcomponent. R₁₂₁ denotes a resistance of the resistance element 121constituting the shunt element 140. C₁₂₂ denotes a capacitance of thecapacitive element 122 constituting the shunt element 140. R₁₂₁ and C₁₂₂constitute the snubber circuit which is the shunt element, and suppressan influence of the voltage bias circuit 180 when viewed from thecircuit of the package 192. The snubber circuit constituted by R₁₂₁ andC₁₂₂ suppresses the parasitic oscillation on the side of a low frequencyof, e.g., not more than several hundred MHz. The package 192 and thevoltage bias circuit 180 are connected to the bias connection terminal181 via the ground connection terminal 182.

FIG. 4 is a view showing an example of an equivalent circuit having aconventional configuration (e.g., Japanese Patent ApplicationPublication No. 2020-136910). As is clear from a comparison between FIG.3 and FIG. 4 , the conventional configuration does not have the shuntelement by the capacitive structure 126, and hence it is difficult toperform impedance adjustment in the medium frequency range. In addition,depending on the circuit configuration and the circuit layout, there isa possibility that the parasitic oscillation caused by the inductorL_(line) may occur.

Thus, by using a plurality of the shunt elements, it becomes easy tosuppress the parasitic oscillation in a wide frequency band. Inparticular, with the capacitive structure 126, it is possible tosuppress the parasitic oscillation in the medium frequency band whichhas been difficult to suppress, and hence the circuit is furtherstabilized.

Second Embodiment

The high-frequency circuit device according to a second embodiment willbe described with reference to FIGS. 5A and 5B to FIG. 7 . Note that thedescription of portions which are common to the above description willbe omitted. FIGS. 5A and 5B to FIG. 7 are views each showing a schematicconfiguration of the high-frequency circuit device 100 according to thepresent embodiment. FIG. 5A is a top view. FIG. 5B is a back surfaceview. FIG. 6A is a cross-sectional view taken along the line A-A′ ofFIG. 5A. FIG. 6B is a cross-sectional view taken along the line B-B′ ofFIG. 5A. FIG. 7 is a cross-sectional view taken along the line C-C′ ofFIG. 5A. As the high-frequency circuit device according to the presentembodiment, an example of an antenna device for transmitting orreceiving a terahertz wave 193 is shown.

The chip 191 in FIG. 6A is different from the first embodiment in thefollowing configuration. The high-frequency element 101 is a negativeresistance element having a gain to the terahertz wave 193. Thehigh-frequency circuit 102 is an antenna for transmitting or receivingthe terahertz wave 193. The antenna can be viewed as a resonancecircuit, and also plays the role of an impedance converter with the air.In particular, in the present embodiment, the chip 191 has a pluralityof the high-frequency elements 101, and one antenna is connected to onehigh-frequency element 101. In the present embodiment, a plurality ofthe antennas are also referred to as an array antenna. In the presentembodiment, power combining of the terahertz wave 193 is performed by anantenna array. As shown in FIG. 5A, the number of chip-side signal pads106 and the number of chip-side ground pads 133 are different from thosein the first embodiment, and four chip-side signal pads 106 and fourchip-side ground pads 133 are disposed. The chip-side signal pad 106 iselectrically connected to the package signal pattern 123 of the package192 via the bonding wire 117. The chip-side ground pad 133 is connectedto the package first ground 125 of the package 192 via the bonding wire117.

The detail of each of the high-frequency element 101 and thehigh-frequency circuit 102 will be described. As the array antenna whichcorresponds to the high-frequency circuits 102, twenty to forty antennasare disposed. FIG. 5A shows an example in which thirty-six antennas aredisposed in a matrix. Note that the arrangement layout is not limitedthereto. In the antenna array used for the purpose of power combining,an interval between the individual antennas is usually set to be notmore than a wavelength which is converted to a wavelength of anoscillating electromagnetic wave in vacuum, or set to be an integralmultiple of the wavelength, or more preferably set to be not more than ahalf of the wavelength. In the present embodiment, the antennas aredisposed such that the interval between the antennas is not more than ahalf of the wavelength of the terahertz wave 193 which is a transmittedelectromagnetic wave.

In the antenna array, a resonance circuit is constituted. The resonancecircuit controls an oscillation frequency with a microstrip resonatorconstituted by a metal layer (corresponds to the high-frequency circuit102) which forms a part of the antenna, the dielectric layer 104, andthe chip ground 103 which is a conductor forming a part of the antenna.The antenna is constituted by the resonance circuit and a negativeresistance element which is the high-frequency element 101. A biasvoltage line which is not shown is connected to the metal layer via thesignal through conductor 120, and a bias voltage is applied to thenegative resistance element. The bias voltage line is connected to thechip-side signal pad 106. The negative resistance element generates anelectromagnetic wave gain for maintaining oscillation. The individualantennas need to oscillate in synchronization with the same phase, andare designed to have a frequency close to an oscillation frequency ω₀.The shapes of the individual antennas each including a half-wavelengthresonator are preferably similar to each other. The present embodimentshows an example of a patch-shaped antenna, but the shape of the antennais not limited thereto. It is preferable to use the negative resistanceelements having shapes and characteristics which are similar to eachother. A configuration in which the antenna also serves as a resonancecircuit for oscillating the electromagnetic wave and the negativeresistance element for supplying power to the resonance circuit isintegrated is also referred to as an active antenna. In particular, theconfiguration of the present embodiment corresponds to an active antennaarray in which a plurality of active antennas are disposed in a matrix.

Each active antenna has a microstrip line (not shown) forsynchronization with the same phase, and adjacent active antennas arecoupled with the microstrip line. In the present embodiment, thismicrostrip line is also referred to as a coupling line for causing theindividual active antennas to oscillate in synchronization with the samephase.

It is preferable to select a length from one end to the other end of thecoupling line which is not shown such that an electrical length of theoscillation frequency ω₀ after the synchronization is 2π. The electricallength of 2π is a length corresponding to an effective oscillationwavelength λ₀ converted with an effective dielectric constant in asurrounding structure. 2π is selected as the electrical length in orderto cause the adjacent active antennas to oscillate in synchronizationwith the same phase. In the case where the adjacent active antennas aresynchronized with the opposite phase, the electrical length may be π or3π. Even when the length of the coupling line is not exactly 2π, it ispossible to synchronize the adjacent active antennas. Although dependingon the size of coupling between elements formed by the coupling line,typically, the electrical length of about 2π±10% is in a permissiblerange. Note that this permissible range is wider than that of a form inwhich the adjacent active antennas are coupled in space without usingthe coupling line. Note that the electrical length of the coupling linecan be easily confirmed with an electromagnetic field simulator or thelike.

A part of an oscillation output of one active antenna is input to theother active antenna positioned adjacent to the one active antenna withsubstantially the same phase via the coupling line. In addition, a partof an oscillation output of the other active antenna is input to the oneactive antenna positioned adjacent to the other active antenna withsubstantially the same phase via the coupling line. In the activeantenna array of the present embodiment, the coupling line is introducedin order to implement a phenomenon of mutual injection locking betweenthe adjacent active antennas.

As an example of the coupling line of the present embodiment, thecoupling line which is not shown is capacitively coupled to a metallayer which is a part of a resonance structure. For example, thecoupling line which is not shown holds an insulating layer between themetal layer and the coupling line to constitute a metal-insulator-metal(MIM) region and forms a capacitance via the insulating layer, and hencethe coupling line is in a DC-open state. With this, in the band of theoscillation frequency ω₀, the size of the coupling between the activeantennas is the same as that of direct coupling, and it is possible tosecure a large size. Further, in a low frequency range which is lowerthan ω₀, the size of the coupling is reduced, and hence it is possibleto secure isolation between the active antennas. Furthermore, in the lowfrequency range which is lower than ω₀, the coupling line which is anopen-ended microstrip line is a capacitive element. When the side of thehigh-frequency circuit 102 which is the metal layer having an antennapattern is viewed from the high-frequency element 101 which is thenegative resistance element, the coupling line is the capacitiveelement, and can function as, e.g., the shunt element. Consequently, aresonance frequency which is a matter of concern in the low frequencyrange is not generated. Accordingly, it becomes possible to suppress theparasitic oscillation in the low frequency range.

Combined power is increased and high directivity can also be obtained bydisposing the active antennas described above in a matrix and couplingthe adjacent active antennas under the above condition of the couplingline in the chip 191, which is preferable.

In FIGS. 5A and 7 , the high-frequency circuits 102 which are aplurality of metal layers are connected in common inside the chip 191via a strip conductor which is not shown, and are connected to thechip-side signal pad 106 to which a bias voltage is applied. Inaddition, the chip ground 103 is connected to the chip-side ground pad133 to which a ground voltage is applied inside the chip 191. With thisconfiguration, when voltage is applied to each of the chip-side signalpad 106 and the chip-side ground pad 133, the bias voltage is applied toeach end of the high-frequency element 101 which is the negativeresistance element.

As the negative resistance element, it is possible to use a resonanttunneling diode (RTD) which lattice-matches an InP substrate. Note thatthe negative resistance element is not limited to the resonant tunnelingdiode, and an Esaki diode or a Gunn diode may also be used. The resonanttunneling diode is configured to have, e.g., a multiple quantum wellstructure with InGaAs/InAlAs and InGaAs/AlAs on an InP substrate, and anelectrical contact layer of n-InGaAs. As the multiple quantum wellstructure, for example, a triple barrier structure is used. Morespecifically, the multiple quantum well structure is constituted by asemiconductor multilayer film structure of AlAs (1.3 nm)/InGaAs (7.6nm)/InAlAs (2.6 nm)/InGaAs (5.6 nm)/AlAs (1.3 nm). Among them, InGaAs isa well layer, and lattice-matching InAlAs and lattice-mismatching AlAsare barrier layers. These layers are undoped layers which are not dopedwith carriers intentionally. The multiple quantum well structuredescribed above is held between the electrical contact layers ofn-InGaAs each having an electron concentration of 2×10¹⁸ cm⁻³. Incurrent-voltage (I/V) characteristics of the structure between theelectrical contact layers, a peak current density is 280 kA/cm², and arange from about 0.7 V to about 0.9 V serves as a negative resistanceregion. In the case where the configuration of the diode adopts a mesastructure having a diameter of 2 μm, a peak current value of 10 mA and anegative resistance value of −20 Ω are obtained. When consideration isgiven to a reactance by the junction capacitance of the resonant tunneldiode having a diameter of 2 μm connected to a lower portion of theantenna pattern constituted by the metal layer, the oscillationfrequency is about 0.3 to 0.6 THz.

In general, at the frequency of the parasitic oscillation to besuppressed, when the impedance of the circuit including a line whenviewed from the negative resistance element is not more than ten timesthe absolute value of a negative differential resistance (e.g., r₁₀₁ inFIG. 3 or FIG. 4 ), the magnitude of a loss caused by the line cannot beignored with respect to a gain of the negative resistance element. Inother words, it is necessary to supply power to the circuit from thenegative resistance element to compensate for lost power, and hencepower contributing to oscillation becomes relatively small, and itbecomes impossible to maintain the oscillation of the parasiticoscillation. The impedance of the circuit including the line ispreferably equal to r₁₀₁, and more preferably has a value less thanr₁₀₁. As an example, in a case where the size of the chip 191 is set toa size of three mm square to four mm square, it is possible to disposetwenty to forty antennas as the high-frequency circuits 102, and thecombined resistance value of the negative resistance of thehigh-frequency element 101 is no larger than 1Ω, i.e., not more than 1Ω.Accordingly, in the frequency range serving as a target, when circuitdesign of the package 192 including the shunt element is performed withthis value used as a target, it is possible to perform the suppressionof the parasitic oscillation. For example, by setting the impedance ofthe package signal pattern 123 to 1Ω or less, the suppression of theparasitic oscillation is facilitated. Herein, the predetermined valueis, e.g., 1Ω.

Next, the package 192 will be described with reference to FIGS. 5A and5B to FIG. 7 . The package 192 is different from the first embodiment inthe following configuration.

The outer dimensions of the package 192 are about 10×8 mm, and thethickness of the package substrate 112 is about 1 mm. The packagesubstrate 112 is an aluminum nitride substrate. With regard to thecavity 110 which accommodates the chip 191 provided on the packagesubstrate 112, the package second ground 114 is disposed on a bottomsurface of the cavity 110. In addition, in this configuration, the backsurface chip ground 107 and the package second ground 114 areelectrically connected to each other on the bottom surface of the cavity110.

In FIG. 5A, the package 192 has four shunt paths 130, and the resistanceelement 121 and the capacitive element 122 which serve as the shuntelement 140 are disposed along each shunt path 130. Two resistanceelements 121 are disposed in parallel. With this, four shunt elements140 are connected in parallel to the high-frequency element 101 servingas the negative resistance element, and it is possible to reduce thecombined impedance of the shunt elements 140. Consequently, thesuppression of the parasitic oscillation is facilitated, and the circuitis stabilized. The number of shunt paths 130 is not limited thereto.

The package 192 has a package floating wiring pattern (package floatingwiring conductor) 135 which is a conductor. The package floating wiringpattern is in a state in which the potential of the package floatingwiring pattern is not determined alone, i.e., the package floatingwiring pattern is in an electrically floating state. The packagefloating wiring pattern 135 also serves as backup wiring and, forexample, when the number of types of the control signal of the chip 191is increased, the package floating wiring pattern 135 is used as aterminal for connection with an external circuit. Alternatively, thepackage floating wiring pattern 135 is space for expanding the circuitinside the package 192. Alternatively, the package floating wiringpattern 135 may also be used as a place for managing the lot number ofthe package 192.

In FIG. 5B, in the package 192, the bias connection terminal 181 and theground connection terminal 182 are disposed on a back surface of thepackage 192. For example, similarly to common SMD components, it ispossible to mount the package 192 in an external circuit with the biasconnection terminal 181 and the ground connection terminal 182. The biasconnection terminal 181 may have a signal pin 131 which is a stick-likeconductor. The ground connection terminal 182 may have a ground pin 132which is a stick-like conductor. In this case, it is possible to handlethe package 192 as a dual inline package (DIP) package, and henceconnection with the external circuit is facilitated. The forms of theseconnection terminals can be appropriately changed according toconnection specifications of the external circuit. With these connectionforms, for example, it becomes easy to manage the impedance of aconnection portion with the voltage bias circuit 180, and hence thecircuit can be expected to be stabilized.

FIG. 6A is a cross-sectional view taken along the line A-A′ of FIG. 5A,and FIG. 6B is a cross-sectional view taken along the line B-B′ of FIG.5A. The package 192 of the present embodiment is different from thefirst embodiment in that the package 192 has a package inner layersignal pattern (package inner layer signal conductor) 119 and a packageinner layer ground 136 which are provided as inner layers in the packagesubstrate 112. For example, the package inner layer signal pattern 119is disposed at a position at which a part of the package signal pattern123 overlaps the package inner layer signal pattern 119 when viewed fromthe package signal pattern 123. Similarly, the package inner layerground 136 is disposed at a position at which a part of the packagefirst ground 125 overlaps the package inner layer ground 136 when viewedfrom the package first ground 125. In addition, in a cross sectionperpendicular to the upper surface of the package substrate 112 or in adirection perpendicular thereto, at least a part of the package innerlayer signal pattern 119 is disposed at a position at which the part ofthe package inner layer signal pattern 119 overlaps at least a part ofthe package signal pattern 123. Similarly, at least a part of thepackage inner layer ground 136 is disposed at a position at which thepart of the package inner layer ground 136 overlaps at least a part ofthe package first ground 125. In addition, in plan view, at least a partof the package inner layer signal pattern 119 is disposed at a positionat which the part of the package inner layer signal pattern 119 overlapsat least a part of the package signal pattern 123. At least a part ofthe package inner layer ground 136 is disposed at a position at whichthe part of the package inner layer ground 136 overlaps at least a partof the package first ground 125. Herein, it is assumed that the planview denotes, e.g., a view in which individual components are projectedonto the package substrate 112 in a vertical direction.

As shown in FIG. 6B, the package inner layer signal pattern 119 isconnected to the package signal pattern 123 and the ground connectionterminal 182 via a package signal through conductor 129. The packageinner layer ground 136 is connected to the package first ground 125, thepackage second ground 114, the package ground 115, and the groundconnection terminal 182 via the package ground through conductor 116.For example, by disposing the package inner layer ground 136 below thepackage first ground 125, it is possible to reduce the impedance of theground layer, and the ground in the circuit is strengthened.Consequently, the circuit is stabilized. In addition, a configuration isadopted in which, below the chip 191, the package inner layer signalpattern 119 is held between the package second ground 114 and thepackage ground 115 which have the same potential. With this, it ispossible to prevent an unnecessary signal noise transmitted in thepackage inner layer signal pattern 119 from being combined with the chip191. Consequently, the circuit is stabilized.

FIG. 7 is a cross-sectional view taken along the line C-C′ of FIG. 5A,and is a cross-sectional view of the capacitive structure 126 along theshunt path 130. The chip signal pattern 105 and the package signalpattern 123 are electrically connected to each other via the bondingwire 117. The capacitive structure 126 is different from the firstembodiment in that the capacitive structure 126 has the package innerlayer signal pattern 119. The package inner layer signal pattern 119 isdisposed inside the base of the package substrate 112 at a position atwhich a part of the package signal pattern 123 overlaps the packageinner layer signal pattern 119 when viewed from the package signalpattern 123 (in a direction perpendicular to the upper surface of thepackage substrate 112). In addition, in plan view, at least a part ofthe package inner layer signal pattern 119 is disposed at a position atwhich the part of the package inner layer signal pattern 119 overlaps atleast a part of the package signal pattern 123. By arranging the signalpatterns in parallel, it is possible to reduce the impedance of wiringand facilitate the suppression of the parasitic oscillation. The packagesignal pattern 123 and the package inner layer signal pattern 119 may beappropriately disposed so as to overlap each other around, e.g., theshunt path 130.

FIG. 8 is an example of an equivalent circuit diagram of the presentembodiment. Unlike the equivalent circuit in FIG. 3 , in the equivalentcircuit diagram in FIG. 8 , with regard to the shunt path 130, aninductor L_(line2) of the circuit of an inner layer including thepackage inner layer signal pattern 119 is connected in parallel to theinductor L_(line) of the circuit of an upper layer including the packagesignal pattern 123. With this, it is possible to decrease the inductorsof the entire circuit. In addition, by having a plurality of thecapacitive structures 126 and a plurality of the shunt elements 140, itis possible to decrease the inductors of the entire circuit.Accordingly, the suppression of the parasitic oscillation isfacilitated, and it is possible to implement the stabilization of thecircuit.

FIGS. 9A and 9B show examples of analysis of the impedance of thepackage 192 of the present embodiment. FIG. 9A is an analysis model. Inorder to analyze the impedance when viewed from the side of the chip191, a port for analysis is provided at the position of the chip 191. Inaddition, the voltage bias circuit 180 is in a disconnected state, andthe bias connection terminal 181 and the ground connection terminal 182are in an open state.

FIG. 9B is a graph of an analysis result, and a real part of theimpedance is plotted in a left graph 91 and an imaginary part of theimpedance is plotted in a right graph 92. The horizontal axis indicatesfrequency, and the vertical axis indicates impedance. Herein, results ofpresence or absence of the capacitive structure 126 and a difference inthe thickness of the base which is a part of the package substrate 112constituting the capacitive structure 126 are plotted. According to theanalysis, it can be seen that values of the real part and the imaginarypart of the impedance are reduced (lowered) by providing the capacitivestructure 126. Specifically, it has been determined that the impedanceof the shunt path 130 can be reduced to 1Ω or less in a frequency band(frequency range) of at least 10 MHz and not more than 10 GHz. Inaddition, it has been determined that the impedance of the shunt path130 can be controlled by changing the thickness of the base of thepackage substrate 112 constituting the capacitive structure 126.

FIGS. 10A and 10B are graphs showing measurement results of theparasitic oscillation for determining the effect of the capacitivestructure 126. FIG. 10A shows a temporal waveform and, in FIG. 10A, thehorizontal axis indicates time, and the vertical axis indicates voltage.FIG. 10B shows a frequency characteristic and, in FIG. 10B, thehorizontal axis indicates frequency, and the vertical axis indicatesamplitude. In FIGS. 10A and 10B, a result in the case where thecapacitive structure 126 is present and a result in the case where thecapacitive structure 126 is not present are compared. According to FIGS.10A and 10B, in the case where the capacitive structure 126 is notpresent, while the parasitic oscillation at about 200 MHz is observed,it can be seen that this parasitic oscillation is suppressed by addingthe capacitive structure 126.

The capacitive structure 126 of the present embodiment is not limited tothe structure which has been described thus far. FIGS. 11A to 11C arecross-sectional views taken along the line C-C′ of FIG. 5A of amodification of the present embodiment. For example, as shown in FIG.11A, the capacitive structure 126 does not need to have inner layerwiring such as the package inner layer signal pattern 119 and thepackage inner layer ground 136 provided above the package second ground114. In addition, as shown in FIG. 11B, in the capacitive structure 126,a part of the package inner layer ground 136 and a part of the packagesignal pattern 123 are disposed so as to overlap each other when viewedfrom the side of the package signal pattern 123, whereby it is possibleto adjust the capacitance of the capacitive structure 126. Further, asshown in FIG. 11C, in the capacitive structure 126, inner layer wiringmay be disposed in a plurality of layers above the package second ground114.

Third Embodiment

The high-frequency circuit device according to a third embodiment willbe described by using FIG. 12 and FIGS. 13A to 13C. Note that thedescription of portions which are common to the above description willbe omitted. The present embodiment is a modification of the embodimentswhich have been described thus far.

FIG. 12 is a cross-sectional view taken along the line A-A′ of FIG. 1Aof the present embodiment. While the chip 191 described above isdisposed inside the cavity 110 provided in the package 192, in thepresent embodiment, the cavity 110 is not used and the chip 191 ismounted on a surface of the package 192 on which the shunt element 140is mounted.

The configuration of the present embodiment is not limited thereto. Forexample, as shown in FIG. 13A, the package 192 may have the inner layerwiring such as the package inner layer ground 136 and the package innerlayer signal pattern 119 which have been described thus far. Inaddition, as shown in FIG. 13B, it is possible to adopt a configurationin which the capacitance of the capacitive structure 126 is adjusted bythe package signal pattern 123 and the package inner layer ground 136.Further, as shown in FIG. 13C, the inner layer wiring may be provided ina plurality of layers in the thickness direction of the packagesubstrate 112.

Fourth Embodiment

The high-frequency circuit device according to a fourth embodiment willbe described by using FIGS. 14A and 14B. Note that the description ofportions which are common to the above description will be omitted. Thepresent embodiment is a modification of the embodiments which have beendescribed thus far. As shown in FIGS. 14A and 14B, the presentembodiment is different from the embodiments which have been describedthus far in that, in a part of an area from the chip 191 to the shuntpath 130, a lumped constant element is disposed in the thicknessdirection of the package substrate 112. For example, in FIG. 14A, acapacitor serving as a lumped constant element 141 which is positionedlateral to the chip 191 is mounted in the thickness direction. In FIG.14A, one terminal of the lumped constant element 141 is connected to thepackage second ground 114, and the other terminal thereof is connectedto the chip-side signal pad 106 and the package-side signal pad 118 withthe bonding wire 117. In addition, as shown in FIG. 14B, it is alsopossible to mount the chip 191 in the lumped constant element 141. InFIG. 14B, one terminal of the lumped constant element 141 is connectedto the package inner layer signal pattern 119, and the other terminalthereof is connected to the back surface chip ground 107 of the chip 191via the conductive layer 111. Note that the lumped constant element 141may also be a lumped constant circuit.

According to the present configuration, it is possible to configure thecircuit in the thickness direction of the package substrate 112, andhence it is possible to increase the number of circuits incorporatedinto the package 192 without changing the size of the package 192. Inother words, it becomes easy to increase the integration degree of thecircuits. In addition, the dielectric of the capacitive structure 126has been limited to the dielectric of the base of the package substrate112 heretofore, but, with the present configuration, it is possible touse a different dielectric material as the capacitive structure 126, andflexibility in circuit adjustment is increased.

Fifth Embodiment

The high-frequency circuit device according to a fifth embodiment willbe described by using FIG. 15 . Note that the description of portionswhich are common to the above description will be omitted. The presentembodiment is a modification of the embodiments which have beendescribed thus far.

In the present embodiment, as shown in FIG. 15 , a sealing layer 134which seals the upper surface of the chip 191 and a part or whole of theupper surface of the package substrate 112 is further provided. As thesealing layer 134, a transparent resin material having a small loss tothe terahertz wave 193 is used. By sealing the surrounding portion ofthe chip 191 which is a heating element with the sealing layer 134, itis possible to diffuse an amount of heat generated by the chip 191 to awide area along the sealing layer 134. Consequently, heat dissipation ofthe chip 191 is improved, and it is possible to prevent thermaldestruction of the high-frequency element 101 constituting the chip 191.

Other Embodiments

While the preferred embodiments and the examples of the presentinvention have been described thus far, the present invention is notlimited to the embodiments and the examples, and can be variouslymodified and changed within the scope of the gist thereof. For example,in the embodiments and the examples described above, the description ismade on the assumption that the carrier is an electron, but the carrieris not limited thereto, and a positive hole (hole) may also be used. Inaddition, the materials of the substrate and the dielectric may beappropriately selected according to uses, and it is possible to usesemiconductors of silicon, gallium arsenide, indium arsenide, andgallium phosphide, glass, ceramic, and resins such aspolytetrafluoroethylene and polyethylene terephthalate. Note that thestructures and the materials described above in the individualembodiments and the individual examples may be appropriately selectedaccording to a desired frequency and the like.

Further, in the embodiments and the examples described above, the squarepatch antenna is used as the resonator of the terahertz wave. However,the shape of the resonator is not limited thereto, and a resonatorhaving a structure which uses a patch conductor having a polygonal shapesuch as, e.g., a rectangle or a triangle, a circular shape, or an oblongshape may also be used.

In addition, the number of differential negative resistance elementsintegrated in the semiconductor element is not limited to one, and theresonator may have a plurality of the differential negative resistanceelements. The number of lines is not limited to one, and a configurationin which a plurality of the lines are provided may also be adopted.

Further, in the above description, as the RTD, the description has beengiven of the double barrier RTD made of InGaAs/AlAs grown on the InPsubstrate. However, the RTD is not limited to these structures andmaterials, and combinations of other structures and materials may alsobe used. For example, the RTD having a triple barrier quantum wellstructure or the RTD having a multiple barrier quantum well structurehaving four or more barriers may also be used.

In addition, as the material of the RTD, each of the followingcombinations may be used.

-   -   GaAs/AlGaAs/and GaAs/AlAs, and InGaAs/GaAs/AlAs formed on a GaAs        sub strate    -   InGaAs/InAlAs, InGaAs/AlAs, and InGaAs/AlGaAsSb formed on an InP        substrate    -   InAs/AlAsSb and InAs/AlSb formed on an InAs substrate    -   SiGe/SiGe formed on an Si substrate

Further, it is possible to use the high-frequency circuit devicedescribed in each of the embodiments and the examples described above asa transmitter in a detection system. For example, the detection systemuses the high-frequency circuit device as the transmitter, and has areceiver which receives a high frequency from the transmitter and aprocessing circuit which processes a signal from the receiver. Thedetection system may also be, e.g., an imaging system which uses theterahertz wave. In addition, in the detection system, the high-frequencycircuit device can also be used as the receiver, and the high-frequencycircuit device can be used as both of the transmitter and the receiver.

According to the present invention, it is possible to suppress theparasitic oscillation.

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2021-209603, filed on Dec. 23, 2021, which is hereby incorporated byreference herein in its entirety.

What is claimed is:
 1. A high-frequency circuit device comprising: a chip which includes a high-frequency element, a high-frequency circuit, a signal conductor, and a chip ground; and a package substrate which includes a base having an upper surface and a back surface on an opposite side of the upper surface, and on which the chip is disposed, the high-frequency circuit device further comprising: a shunt path which is constituted by a package signal conductor which is disposed on the upper surface of the package substrate and is electrically connected to the signal conductor, a package first ground which is electrically connected to the chip ground, and a shunt element which is electrically connected to the package signal conductor and the package first ground; and a package second ground which is disposed at least inside the base of the package substrate or on the back surface of the package substrate, wherein a part of the base, a part of the shunt path, and the package second ground constitute a capacitive structure.
 2. The high-frequency circuit device according to claim 1, wherein a frequency range in which an impedance of the shunt path is made equal to or less than a predetermined value by the capacitive structure is a range of at least 10 MHz and not more than 10 GHz.
 3. The high-frequency circuit device according to claim 2, wherein the impedance of the shunt path is not more than 1Ω in the range of at least 10 MHz and not more than 10 GHz.
 4. The high-frequency circuit device according to claim 1, further comprising: a package ground which is disposed on the back surface of the package substrate.
 5. The high-frequency circuit device according to claim 4, wherein the chip further has a chip ground through conductor and a back surface chip ground, the chip ground through conductor connects the chip ground disposed on an upper surface of the chip and the back surface chip ground disposed on a back surface of the chip, and the back surface chip ground is connected, via a conductive layer, to the package second ground of the package substrate or the package ground of the package substrate.
 6. The high-frequency circuit device according to claim 1, further comprising: a package ground through conductor which connects the package first ground and the package second ground, wherein, in a case where an effective wavelength of a high-frequency signal of the high-frequency circuit is a wavelength λ_(sig) and an effective wavelength of parasitic oscillation which occurs in the shunt path is a wavelength λ_(para), a distance L between the high-frequency element and the package ground through conductor satisfies λ_(sig)≤L≤λ_(para).
 7. The high-frequency circuit device according to claim 1, further comprising: a package inner layer signal conductor which is disposed inside the base of the package substrate at a position at which a part of the package inner layer signal conductor overlaps the package signal conductor in a direction perpendicular to the upper surface of the package substrate.
 8. The high-frequency circuit device according to claim 1, wherein a part of the shunt path, a part of the package first ground, and a part of the package second ground are disposed so as to overlap each other in a case where viewed from the shunt path.
 9. The high-frequency circuit device according to claim 1, wherein the package substrate further has a cavity which accommodates the chip, and the back surface chip ground disposed on the back surface of the chip and the package second ground are electrically connected to each other on a bottom surface of the cavity.
 10. The high-frequency circuit device according to claim 1, wherein the signal conductor and the package signal conductor are electrically connected to each other via a wire.
 11. The high-frequency circuit device according to claim 1, wherein a lumped constant element is disposed in a thickness direction of the package substrate in a part of an area from the chip to the shunt path.
 12. The high-frequency circuit device according to claim 1, further comprising: a sealing layer which seals the upper surface of the chip and a part or a whole of the upper surface of the package substrate.
 13. The high-frequency circuit device according to claim 1, wherein the chip is disposed on the upper surface of the base.
 14. The high-frequency circuit device according to claim 1, wherein the high-frequency element is a negative resistance element, and the high-frequency circuit is an antenna which transmits or receives a terahertz wave.
 15. A detection system comprising: the high-frequency circuit device according to claim 1 which is used as a transmitter; a receiver which receives a high frequency from the transmitter; and a processing circuit which processes a signal from the receiver. 